`include "defines.v"

module ex_mem(
    input  wire                      clock,
	input  wire                      reset,
	input  wire[`RegisterAddressBus] ex_wd,
	input  wire                      ex_wreg,
	input  wire[`RegisterBus]        ex_wdata,
	input  wire[`RegisterBus]        ex_hi,
	input  wire[`RegisterBus]        ex_lo,
	input  wire                      ex_hilo_we,
	input  wire[`STALL_BUS]			 stall,
	output reg[`RegisterBus]		  mem_hi,
	output reg[`RegisterBus]		  mem_lo,
	output reg					  mem_hilo_we,
	output reg[`RegisterAddressBus]  mem_wd,
	output reg                       mem_wreg,
	output reg[`RegisterBus]         mem_wdata
);

    always @ (posedge clock) begin
	    if (reset == `ResetEnable) begin
		        mem_wd <= `NOPRegisterAddress;
				mem_wreg <= `WriteDisable;
				mem_wdata <= `ZeroWord;
				mem_hi <= `ZeroWord;
				mem_lo <= `ZeroWord;
				mem_hilo_we <= `ZeroWord;
		end else if(stall[3] == 1'b1 && stall[4] == 1'b0)begin
				mem_wd <= `NOPRegisterAddress;
				mem_wreg <= `WriteDisable;
				mem_wdata <= `ZeroWord;
				mem_hi <= `ZeroWord;
				mem_lo <= `ZeroWord;
				mem_hilo_we <= `ZeroWord;
		end else if(stall[3] == 1'b0) begin
		        mem_wd <= ex_wd;
				mem_wreg <= ex_wreg;
				mem_wdata <= ex_wdata;
				mem_hilo_we <= ex_hilo_we;
				mem_hi <= ex_hi;
				mem_lo <= ex_lo;
		end
	end

endmodule